Leading Electronics and EDA Companies Rally Together in Support of Accellera Formal Property Language
Open Standard will Enable New Generation of Electronics Verification Tools, Libraries, and Methodologies United Around a Single Language
SAN JOSE, Calif. - April 25, 2002 - Several leading electronics and electronic design automation (EDA) companies today pledged support for the formal property language recently selected by the Accellera Formal Verification Technical Committee. The Committee selected the Sugar formal property language from IBM. The language is the industry's first standard for formal properties and was chosen after months of careful deliberation and debate by members of the Technical Committee, representing a wide variety of electronics and EDA companies.
Companies rallying behind the language include 0-In Design Automation, Inc.; @HDL, Inc.; Cadence Design Systems, Inc.; Co-Design Automation, Inc.; Galileo Technology - a Marvell Company; IBM; Infineon™ Technologies; Mellanox™ Technologies, Ltd.; Mentor Graphics Corporation; NoBug Consulting; Novas Software, Inc.; Real Intent™; Structured Design Verification Inc.; TNI-Valiosys; TransEDA PLC; Veritable Inc.; Verplex™ Systems Inc.; and Zoran Corporation.
The creation of the language is a collaborative action within the electronics industry aimed at enabling a new generation of verification tools, libraries, and methodologies united around the single language. Widespread adoption of the Accellera language would mean a huge leap in productivity for EDA vendors and customers alike, as vendors can focus their resources to develop tools for a single formal property language, and customers can focus on using a common standard for developing property libraries that can be reused with tools from multiple vendors.
"The Accellera Formal Verification Technical Committee defined an open, transparent, and fair process that led to the selection of Sugar as the new industry-standard formal property language," said Harry Foster, chairman of the Technical Committee. "The standard offers an opportunity to enable a huge leap in productivity in electronics design and verification. It is critical that the electronics industry now rally around the language, and develop and demand tools based on it."
Electronics and EDA Company Representatives Declare Support
"Rapid finalization and adoption of the Accellera formal property language standard is key to EDA tool interoperability and widespread adoption of assertion-based verification. The new Accellera formal property language has the right balance of expressiveness for formal verification tools and intuitiveness for users. 0-In is committed to supporting the Accellera standard and will soon have a version of its CheckerWare™ Library and Monitors which incorporates it, enabling interoperability with any tool that supports the standard."
-Tom Anderson, vice president of applications engineering, 0-In Design Automation, Inc.
"@HDL is committed to support the evolving standardization efforts in the area of assertion-based and formal methods. We applaud the rigorous and collaborative process that has resulted in this standard. Our products will support this standard to deliver significant productivity improvement to the design and verification community."
-Badru Agarwala, president and CEO, @HDL, Incorporated
"Accellera's member companies have laid down a clear, industry wide verification standardization strategy which Co-Design Automation actively supports today. The new property language specification draft enables a key element of an effective verification platform that may be applied across a range of validation technologies."
-David Kelf, vice president of marketing, Co-Design Automation, Inc.
"Galileo has a long record of successfully utilizing the selected property language Sugar. We look forward to the EDA industry embracing the standard, and thus improving the compatibility of different tools and methodologies."
-Sagi Katz, formal verification group manager, Galileo Technology - A Marvell Company
"We're pleased that Sugar, which has been advantageously used by IBM for eight years, has now been accepted for standardization by Accellera. This is a true milestone for the EDA and chip design industries. Accellera's selection of Sugar as the standard property language will pave the way for designers and engineers to more easily develop and deploy advanced verification tools, thereby enabling them to focus on providing competitive advantages to their customers."
-Dr. Yaron Wolfsthal, manager of formal methods, IBM Research Labs, Haifa, Israel
"The Accellera Formal Verification Committee has selected IBM Sugar as the standard for the industry. The Committee with experts from industry and academia has analyzed several donated languages with respect to detailed requirements and also based on formal verification science. Now the standard is ready for prototyping and use in tools and designs with the release of the LRM in May. Infineon supports the selection and use of the Accellera Sugar language as the only standard in the industry for formal property specification."
-Vassilios Gerousis, design system architect, Infineon Technologies, and technical chairman of all Accellera committees
"We have been using the Sugar formal verification language successfully for several years. Our formal verification engineers have found Sugar to be a very intuitive language, capable of describing a wide range of specifications in a concise and compact way. Sugar has a major role in our verification flow, and we are investigating new ways to widen its application."
-Roni Ashuri, vice president of engineering, Mellanox Technologies, Ltd.
"We need an open industry standard property language that will dramatically enable the EDA industry to deliver better verification solutions. Therefore, we strongly support the Accellera initiative."
-Brian Derrick, vice president of corporate marketing, Mentor Graphics Corporation
"Sugar, IBM's formal property language, has been used by our formal verification engineers since October 2000. As NoBug is taking responsibility for verifying some of the most complex designs in the ASIC industry, the use of Sugar provides us with the needed ease-of-use, depth, flexibility, and expressiveness. It has been very effective in our verification service engagements. We are happy that Sugar is now going to be made available to the entire semiconductor industry as an Accellera standard. We plan to expand activities related to the new standard, both in services and EDA development."
-Moshe Shalev, CEO, NoBug Consulting
"Properties are vital to the future of verification. A standard property language is one of the keys to actually putting property-based verification methods into practice. We will support properties in our debug systems, and we fully support the Accellera standards effort and the emerging formal property language."
-Scott Sandler, president and CEO, Novas Software, Inc.
"We are firmly behind the Accellera effort for an industry-standard formal property language, and have demonstrated our commitment by contributing our IP to accelerate this process. This standardization effort will deliver enormous benefits as it elicits broadest support from tool vendors, both established and emerging, and it is applicable across different technologies such as formal and simulation, providing choices to the widest customer base."
-Dr. Prakash Narain, president and CEO, Real Intent
"We need a compact, expressive language to describe temporal relationships for our forthcoming interface generation tools and in particular a language that will be re-useable across a broad range of verification tools. We've actively participated in the Accellera formal verification effort and are pleased with this decision which allows us to radically improve users' productivity when describing interface protocols. Our first tools are already being modified to support the Accellera-endorsed language and will be shipped later this year."
-Bernard Deadman, CEO, Structured Design Verification Inc. (SDV)
"It is only through working together as an industry that we will successfully address the verification crisis that confronts us today. TransEDA will support Accellera's formal property language in the next release of our VN-Property DX™ dynamic property checker and in formal and semi-formal tools currently under development. We urge all EDA vendors to support the Accellera standard, and urge customers to demand these tools. Widespread adoption of this standard by EDA vendors will benefit our customers and in turn the industry as a whole."
-Ellis Smith, chief executive officer, TransEDA PLC
"Veritable is happy to endorse the release of a formal property language by Accellera and is planning to offer support for the language in its Verity-Check property checker. The release of a standard property specification language is an important step forward for the electronics industry and provides a good opportunity for the industry to unite and put an early end to the formal verification language wars before the different sides get too firmly entrenched in their positions."
-Prab Varma, president, Veritable Inc.
"We applaud the open and democratic means by which the Accellera standard language was selected. Verplex has made the commitment to support the language with its BlackTie™ functional checker. The language's rich, powerful constructs make it ideal for specifying complex properties, thereby extending its application to even higher levels of abstraction and into a broader range of verification methodologies."
-Dr. Kuang-Chien (KC) Chen, chief technology officer and senior vice president of R&D,
Verplex Systems Inc.
"Zoran Corporation is a leading provider of digital solutions-on-a-chip in the growing multimedia and consumer electronics markets. During the last 4 years we have been using formal verification methods, specifically Rule-Base from IBM that is based on the Sugar language. We found that using formal verification was one of the major reasons for having very complex SoCs ready for production at the first step."
-Avi Parash, director of IP solutions, Zoran Microelectronic LTD.
About the Companies Mentioned in this Press Release
Note: 0-In is a registered trademark and CheckerWare is a trademark of 0-In Design Automation, Inc. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. IBM and the IBM logo are registered trademarks of IBM Corporation. Infineon and the stylized Infineon Technologies design are trademarks and servicemarks of Infineon Technologies AG. Mellanox is a trademark of Mellanox Technologies, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Novas Software is a registered trademark of Novas Software, Inc. Real Intent is a trademark of Real Intent. TransEDA is a registered trademark and VN-Property DX is a trademark of TransEDA PLC. Verplex and BlackTie are trademarks of Verplex Systems Inc. Zoran is a registered trademark of Zoran Corporation. All other trademarks are the property of their respective holders.
Media Contact:
Jen Bernier
Armstrong Kendall, Inc.
415.824.1026
jen@akipr.com
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